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Currently, only JLINK is supported with OpenOCD using additional JTAG connection.
The main reasons are:
1. DAPLINK cannot be used to debug non-arm core according to the license of CMSIS-DAP.
2. JTAG support isn’t included in the latest official cmsis-dap implementation.A low-cost debugger that is compatible with the VEGAboard is the SEGGER J-Link EDU Mini.
Hope this clears up any confusion!
Regards,
AlexHello,
My board is on the go, but I don’t have yet bought the J-Link JTAG adapter.
According to Segger website there is several other models: https://www.segger.com/products/debug-probes/j-link/models/model-overview/Could you please confirm all of them are compatible, or should we care on some specific model (and not only the cheapest one)?
Regards,
Phil
They are all compatible but going beyond the EDU mini doesn’t really make sense for this board. The more expensive ones download code faster, which is useful if you are flashing large code multiple times a day. The other ones have a higher interface and bandwidth speeds which again probably wouldn’t be useful. I’ve tried out 3 different JTAG programmers (jlink, FTDI and Altera blaster) and they see the vega board no problem.
Main reason is that DAPLINK cannot be used to debug non-arm core according to the license of CMSIS-DAP. And the JTAG support isn’t included in the latest official cmsis-dap implementation.
If someone has a standalone debugger running daplink firmare with JTAG support, he can use it to debug RISC-V core just for try and test by changing the interface from jlink to cmsis-dap in the .cfg file under boards/rv32m1_vega folder.
Regards,
HowardI have managed to establish connection with the board via cmsis-dap interface but cant flash program any code as halt command fails every time. As mentioned above cmsis-dap works with arm cores, I should be able to program on M0 and M4 cores of the board, right?
Do you have the RV32M1 target in build for the cmsis-dap? That may be why it can’t halt the CPU
Yes I have. This is my target in openocd config file:
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAMESorry target config mentioned above gives this error:
openocd: src/jtag/core.c:343: jtag_checks: Assertion `jtag_trst == 0′ failed.But this works:
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0I only need to flash binaries to the Vegaboard, I currently have no need for debug capabilities.
After reading parts of the reference manual, I found that the Kinetis Bootloader is available in ROM. Unfortunately, I cannot see an USB connection of the bootloader over the native USB port of the Vegaboard with holding the NMI button while plugging in.
Additionally, the flash drive emulation on the OpenSDA USB connector does accept memory images for ARM in the pop-up drive, but reports a fail afterwards. I tried with raw binary, intel hex and motorola srec format, but with no luck. The board continues to run the accelerometer demo; at least, it should have crashed after writing a different binary.
I am using Debian stable OS, may I have to update the OpenSDA firmware for the drag-and-drop flashing to work ?
Regarding RISC-V, it seems as if the ARM bootloader could fill the flash memory after a full erase, and a snipplet of ARM code could change the FOPT contents afterwards. Another idea would be to use the M4/Zero-Riscy combination.
I’m looking for a wiring/connection diagram of J-Link Base to the host and VEGA. I know it’s a basic question, but I’ve never used these tools. Thanks.
I bought a Segger J-Link Plus and checked with Segger support. The connection is correct. I get this error message from Eclipse when I run Debug.
Open On-Chip Debugger 0.10.0+dev-00432-gfdd28b5a (2018-12-25-08:25)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
Info : mohor tap selected
Info : adv debug unit selected
Info : Option 1 is passed to adv debug unit
Info : core 0 selected
Info : add flash_bank rv32m1 rv32m1.flash0
Info : add flash_bank rv32m1 rv32m1.flash1
Warn : Failed to open device: LIBUSB_ERROR_NOT_SUPPORTED.
Error: No J-Link device found.Warn : Flash driver of rv32m1.flash0 does not support free_driver_priv()
Warn : Flash driver of rv32m1.flash1 does not support free_driver_priv()The Eclipse pop up displays this error:
OpenOCD failed with code (1).For more details, see the openocd.exe console.
Hi WoolyBugger2019,
Please navigate to
\Toolchain_Windows\openocd\drivers and open UsbDriverTool.exe. Once that opens, with your J-Link plugged in, right click on “J-Link driver” and select “Install WinUSB”. Please visit our Getting Started section for a step by step guide on how to set up your environment and flash your first program on the VEGAboard.
Let me know if you are still having this issue.
-Alex
Dear Alex
A big thanks to you. Yes, that was the problem. It works!I bought the J-Link debugger and connected it AFTER I already installed all the GCC and Eclipse software dev environment per the Getting Started Guide. I was able to build in both GCC command line and Eclipse no problem.
Does j-Link v8 supports debugging RISC-V core of this board?
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