A few questions arose:
* For getting LPUART0 up and running, I set PORTC_PCR7 and PORTC_PCR8 to alternate 3, switched on PCC_LPUART0 with SYS OSC source (should be 48 MHz FIRC on boot, reset clock configuration not changed) and configured LPUART0_BAUD and LPUART0_CTRL. But I could not see characters coming out when writing LPUART0_DATA. Did I miss another register which needs to be set for initialisation of LPUART0 ? Bit-bang communication using PC7 and PC8 as GPIO lines is fine.
* What could happen with two 4 byte back-to-back flash writes into one aligned 8 byte location using the “program phrase” command 7, with the already programmed word set to $FFFFFFFF ? Does it slowly damage the memory due to overstress by applying the programming voltage twice; or does it simply result in less-than-specified data retention, which is okay for first testing purposes ? The reference manual specifies one write cycle is allowed into each aligned 8 byte section for primary flash.
* I know the supplied example code package using libraries is common for large chips like the RV32M1, but as a variety of languages are to be ported to RISC-V, I would greatly appreciate simple low-level examples in assembler or at least in C with direct register access, without any library usage. Please don’t be angry with me for referencing another manufacturer; but the example package for MSP430F2012 by TI given at http://www.ti.com/lit/zip/slac080 is exactly what I would wish for the Vega, at least for the basic peripherals like GPIO, clock distribution, interrupts, sleep mode, timers, UART, ADC. It would greatly simplify launching the non-C ecosystem for the new architecture.